Fuse trimming for trimming a reference current with a fuse has been performed heretofore in order to obtain intended characteristics, regardless of characteristic unevenness due to increasing production unevenness of semiconductor integrated circuits along with miniaturization thereof.
FIG. 10 illustrates a reference current source circuit 105 having a fuse 101 and a current source circuit 102 for fuse trimming.
With the reference current source circuit 105, it is readily understood that a state of a semiconductor integrated circuit after disconnection of the fuse 101 cannot be measured before disconnection of the fuse 101. Therefore, it is necessary to measure characteristic unevenness of the semiconductor integrated circuit by other method in order that a state after disconnection of the fuse 101 may be predicted.
For measuring characteristic unevenness of a semiconductor integrated circuit, there is a method with a monitoring device including a resistor and capacitor formed on a wafer. In this method, it is possible to predict a state after disconnection of a fuse by measuring the characteristic unevenness of the resistor and the capacitor of the monitoring device.
However, some errors would be observed in this method in comparison with an actual state obtained after disconnection of the fuse because the method is ultimately for prediction. In addition, it is impossible to consider in-plane characteristic unevenness of the wafer because only a few monitoring devices are normally provided on the wafer. Furthermore, it is impossible to detect subtle characteristic errors caused due to a mismatch of elements. Accordingly, chances of incorrect fuse trimming are high in a case where fuse trimming is performed with the reference current source circuit 105. A product actually becomes defective due to such incorrect fuse trimming.
FIG. 11 schematically illustrates a structure of a MOS analog integrated circuit shown in Publication 1 (Japanese Unexamined Patent Publication: Tokukaisho 61-114319 (published on Jun. 2, 1986)).
In the MOS analog integrated circuit, a bias voltage is supplied with an analog circuit A by controlling a switch SW which is a MOS transistor of a bias circuit B according to a control signal C which is supplied from a control circuit D and whose level becomes high in response to disconnection of a fuse. In the MOS analog integrated circuit with this structure a state after disconnection of the fuse can be measured before disconnection of the fuse, not by disconnection of the fuse, but by feeding the control signal C at H level.
However, this structure has a problem in that extra consumption current is consumed because extra current Ix flows through a resistor Rx when fuse trimming is completed without disconnection of the fuse.
FIG. 12 illustrates a fuse trimming circuit shown in Publication 2 (Japanese Unexamined Patent Publication: Tokukaihei 3-4187 (published on Jan. 10, 1991)). Table 1 describes the operation of this fuse trimming circuit.
TABLE 1CONTROLENABLESIGNAL DSW1SW20—ONOFFNORMAL MODE10OFFONTEST MODE: FUSE NOTDISCONNECTED11OFFOFFTEST MODE: FUSEDISCONNECTED
As shown in “test mode” in Table 1, by controlling switches SW1 and SW2 with an Enable signal and a control signal D, the fuse trimming circuit above can be measured as to its state with disconnection of the fuse and a state without disconnection of the fuse, that is, the state after fuse trimming. For the structure above, however, two switching circuits are required and thus this causes a problem in that the number of circuit elements increases. In addition, the structure above also has a problem in that the Enable signal needs to be always supplied from outside in order to maintain the state of normal operation.